Conventionally, an SOI MOS transistor has a sectional structure shown in FIG. 1 or 2. Referring to FIGS. 1 and 2, reference numeral 1 denotes a silicon substrate; 2, an SiO.sub.2 film; 3, a monocrystalline silicon film; 4, an n.sup.+ -type region; 5, a gate insulating film; 6, a polysilicon gate; and 7, a depletion layer.
FIG. 1 shows a MOS transistor wherein the monocrystalline silicon film 3 is relatively thick, i.e., a non-depletion region is left under a channel region. In this case, since a gate electric field is applied to both the gate oxide film 5 and the depletion layer 7, the field intensity of a channel region is increased. For this reason, in the MOS transistor, the field effect mobility of electrons is decreased since the crystallinity of the monocrystalline silicon film 3 is inferior to that of the silicon substrate (bulk silicon) 1, and current drivability is disadvantageously degraded.
FIG. 2 shows a MOS transistor wherein the thickness of the monocrystalline silicon film 3 is relatively small, about 500 .ANG., i.e., an entire portion under the channel region is depleted. In this case, a depletion layer formed in the monocrystalline silicon film 3 reaches the underlying SiO.sub.2 film 2. For this reason, a capacitance between the monocrystalline silicon film (p-type, in general) 3 and the n.sup.+ -type region 4 is decreased, and the field effect mobility of electrons is advantageously increased to be 900 to 1000 cm.sup.2 /V.multidot.S which is larger than 1.5 times that of a bulk MOS transistor.
In a MOS transistor having the relatively thin monocrystalline silicon film 3, when the monocrystalline silicon film 3 is further thinned, the field effect mobility of electrons can be closed to the mobility (1,350 cm.sup.2 /V.multidot.S) of electrons flowing through the silicon substrate. This is described in "Characteristic Analysis of High-Performance SOI.multidot.MOSFET Using Thin Film SOI" by Makoto Yoshimi, et al., transactions (silicon material.device) of the Institute of Electronics and Communication Engineers of Japan, SDM 87-154, pp. 13-18, Jan., 1988.
As shown in FIG. 3, when a contact hole reaching the n.sup.+ -type region 4 serving as a drain or source is formed in an insulating interlayer 8 by anisotropic etching such as RIE (Reactive Ion Etching), as the monocrystalline silicon film 3 is thinned, a probability of etching the SiO.sub.2 film 2 to form a contact hole extending through the n.sup.+ -type region 4 is increased. In this case, compared with a case wherein a contact hole does not extend through the n.sup.+ -type region 4, the area of the contact portion between the Al electrode 9 and the n.sup.+ -type region 4 is decreased by .pi.r.sup.2 -2.pi.rd=.pi.r.sup.2 (1-2d/r) where r is the radius of the cylindrical contact hole and d is the thickness of the monocrystalline silicon film 3. In this case, r&gt;2d must be satisfied. That is, as the thickness d of the monocrystalline silicon film 3 is decreased, the area of the contact portion between the Al electrode 9 and the n.sup.+ -type region 4 is decreased, thereby disadvantageously increasing its contact resistance. Note that, when wet etching is performed by NH.sub.4 F or the like in place Of RIE, the above-mentioned excessive extension of the contact hole can be prevented. However, a margin for contact alignment must be sufficiently obtained. This adversely affects high integration.
When the monocrystalline silicon film 3 is thinned, a diffusion layer formed thereon must also be thinned, thereby increasing the resistance of the diffusion layer wiring. For this reason, even when the monocrystalline silicon film 3 is thinned to increase the field effect mobility of electrons so as to increase the current drivability, a high-speed operation as an integrated circuit cannot be expected. Therefore, the diffusion layer wiring cannot be used. The wiring of the integrated circuit must comprise only an Al wiring film and a gate polysilicon layer, and a degree of freedom of design is limited, thereby disadvantageously increasing the pattern.
It is an object of the present invention to provide a high-speed, high-performance, and high-quality SOI semiconductor device which is manufactured without increasing a contact resistance and a wiring resistance of a diffusion layer even in an SOI.multidot.MOS integrated circuit having a thin monocrystalline silicon film.